cy7c106bn 256k x 4 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06429 rev. *a revised march 15, 2010 features high speed ? t aa = 15 ns cmos for optimum speed/power low active power ? 495 mw low standby power ? 275 mw 2.0v data retention (optional) automatic power down when deselected ttl-compatible inputs and outputs functional description the cy7c106bn is a high performance cmos static rams organized as 262,144 words by 4 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tristate drivers. these devices have an automatic power down feature t hat reduces power consumption by more than 65% when the devices are deselected. writing to the devices is accomp lished by taking chip enable (ce ) and write enable (we ) inputs low. data on the four i/o pins (i/o 0 through i/o 3 ) is then written into the location specified on the address pins (a 0 through a 17 ). reading from the devices is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pi ns will appear on the four i/o pins. the four input/output pins (i/o 0 through i/o 3 ) are placed in a high impedance state when the devices are deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce and we low). the cy7c106bn is available in a standard 400-mil-wide soj. 512 x 512 x 4 array a 1 a 0 10 12 11 13 14 column decoder row decoder sense amps power down oe input buffer 15 16 17 we ce i/o 0 i/o 1 i/o 2 i/o 3 a 2 a 3 a 4 a 6 a 7 a 8 a 9 a 5 logic block diagram [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 2 of 9 pin configuration figure 1. 28-pin soj (top view) 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 12 13 25 28 27 26 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 17 v cc a 16 a 15 a 14 a 13 i/o 3 i/o 2 i/o 1 i/o 0 a 9 a 0 a 10 ce oe nc a 12 a 11 we selection guide description 7c106bn-15 maximum access time (ns) 15 maximum operating current (ma) 80 maximum standby current (ma) 30 [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 3 of 9 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65c to +150c ambient temperature with power applied ........................ ................... ?55c to +125c supply voltage on v cc relative to gnd [1] .....?0.5v to +7.0v dc voltage applied to outputs in high z state [1] .................................... ?0.5v to v cc + 0.5v dc input voltage [1] ................................ ?0.5v to v cc + 0.5v current into outputs (low)..... .................................... 20 ma static discharge voltage ...... ........... ............ .............. >2001v (per mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c106bn-15 min max unit v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ma i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ma i os output short circuit current [3] v cc = max, v out = gnd ?300 ma i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 80 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f=0 commercial 10 ma capacitance [4] parameter description test conditions max unit c in : addresses input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 7pf c in : controls 10 pf c out output capacitance 10 pf notes 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. not more than 1 output should be shorted at one time. du ration of the short circuit should not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 4 of 9 figure 2. ac test loads and waveforms switching characteristics over the operating range [5] parameter description 7c106b-15 min max unit read cycle t rc read cycle time 15 ns t aa address to data valid 15 ns t oha data hold from address change 3 ns t ace ce low to data valid 15 ns t doe oe low to data valid 7 ns t lzoe oe low to low z 0 ns t hzoe oe high to high z [6, 7] 7 ns t lzce ce low to low z [7] 3 ns t hzce ce high to high z [6, 7] 7 ns t pu ce low to power up 0 ns t pd ce high to power down 15 ns write cycle [8, 9] t wc write cycle time 15 ns t sce ce low to write end 12 ns t aw address setup to write end 12 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 12 ns t sd data setup to write end 8 ns t hd data hold from write end 0 ns t lzwe we high to low z [7] 3 ns t hzwe we low to high z [6, 7] 7 ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30 pf load capacitance. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady stat e voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and hol d timing should be referenced to the leading edge of the sig nal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r1 480 r1 480 r2 255 r2 255 167 equivalent to: th venin equivalent 1.73v rise time < 1v/ns fall time < 1v/ns [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 5 of 9 data retention characteristics over the operating range parameter description conditions [10] min max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 250 a t cdr [4] chip deselect to data retention time 0 ns t r [4] operation recovery time 200 ms figure 3. data retention waveform 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r switching waveforms figure 4. read cycle no.1 [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] notes 10. no input may exceed v cc +0.5v. 11. device is continuously selected, oe and ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 1 previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance impedance i cc i sb t hzoe t hzce t pd high address ce data out v cc supply current oe [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 6 of 9 figure 6. write cycle no. 1 (ce controlled) [14, 15] figure 7. write cycle no. 2 (we controlled, oe high during write) [14, 15] notes 14. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 15. data i/o is high impedance if oe = v ih . switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 7 of 9 figure 8. write cycle no. 3 (we controlled, oe low) [9, 15] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o truth table ce oe we input/output mode power h x x high z power down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 15 cy7c106bn-15vc 51-85032 28-pin (400-mil) molded soj commercial contact your local sales representative regarding availability of these parts. [+] feedback
cy7c106bn document #: 001-06429 rev. *a page 8 of 9 package diagram figure 9. 28-pin (400 mil) molded soj 51-85032-*b pin 1 i.d .435 .395 .445 .405 .128 .148 .026 .015 .032 .020 dimensions in inches min. max. .025 min. .050 typ. .720 .730 1 14 8 2 5 1 0.004 seating plane .360 .380 .007 .013 no chamfer notes : 1. package weight : 1.24g 2. jedec reference : ms-027 51-85032.*d [+] feedback
document #: 001-06429 rev. *a revised march 15, 2010 page 9 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c106bn ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy7c106bn 256k x 4 static ram document number: 001-06429 rev. ecn no. submission date orig. of change description of change ** 423847 see ecn nxr new data sheet *a 2891262 03/12/2010 vkn removed cy7c1006bn part from the data sheet removed industrial grade removed 20ns speed bin removed 28-pin (300-mil) molded soj package updated pod for 28-pin (400-mil) molded soj package updated ordering information table updated urls in sales, solutions, and legal information [+] feedback
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